Forum:How to synthesize using verilog

hi, i created a verilog module ...i compiled and run using iverilog...and also able to generate vcd file to verify the functional simulation using gtk......

1.how to synthasize the module using iverilog... 2. in the wiki mentioned that some projects listed....but i am unable to see the project list.. what projects are there could please give the link there i can find the projects....

thanks & regards rameshlv